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Issue #209 December 2007
THE DARKER SIDE
Are You Locked?
A PLL Primer
by Robert Lacoste
Start | VCO Basics | PLL Basics | Integer or Fractional? | PLL Design | Silicon Trends | It's Your Turn! | Sources & PDF
INTEGER OR FRACTIONAL?
The PLL architecture in Figure 6 is called an integer-N PLL. It is a simple and elegant architecture, and you can use it to generate any frequency that can be expressed as N × FIN/R. Suppose that you have a 10-MHz reference frequency and you want to be able to tune the PLL output around 500 MHz with a resolution of 1 kHz. The 1 kHz is called the channel spacing. Then the solution will be to set the R divider to 10,000 (i.e., 10 MHz/1 kHz). FOUT is N × FIN/R, which translates to N × 1 kHz. So the PLL will generate a 500-MHz signal if you set N = 500,000 or a 500 MHz + 1-kHz signal with N = 500,001, and so on.
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| Figure 6—The architecture of a PLL is built around a phase detector that drives a voltage-controlled oscillator through a filtering stage. The output of the VCO is then looped back to the phase detector and compared to a reference frequency. Dividers enable you to change the frequency ratio between the reference and output. So-called “fractional-N” PLLs have the same architecture but allow noninteger dividers. |
So, with an integer-N PLL, the rule is that the PFD frequency must be equal to the desired channel spacing. The required channel is then selected with the N divider. Such chips are used in plenty of products, but they have two fundamental issues linked to the rule. The first is lock time. In the previous example, the desired channel spacing was 1 kHz, giving a 1-kHz PFD frequency. Because the output of the PFD contains spikes of energy at the 1-kHz frequency, the low-pass filter between the PFD and the VCO must have a cutoff frequency significantly lower than 1 kHz in order to reject this noise. Typically, a good starting point is to set the loop filter bandwidth at 10% of the PFD frequency, so let’s assume we use a 100-Hz filter. What happens if you reprogram the N divider to switch the PLL to another frequency? The output of the PFD will change, but this analog signal will have to pass through the 100-Hz low-pass filter prior to changing the VCO frequency, and this will take time because the filter is filtering out all quick variations. The PLL will lock to the new frequency, but probably some hundreds of milliseconds later. So, with an integer-N PLL, you will have the choice between small frequency steps and fast lock time, but not both.
The second issue with integer-N PLLs is a little less straightforward and related to phase noise. Basically, a PLL “multiplies” the PFD frequency by N. As you have seen, in order to have small frequency steps, you need a low PFD frequency, which means you need high values for N. Unfortunately, the phase detector is not a perfect device, so it generates some phase noise, which is unfortunately multiplied by N. Trust me, the PFD noise is increased by 20log(N) in decibels, so it is far higher if you need to increase the N divider ratio. With an integer-N PLL, small frequency steps will always mean a more noisy output and a longer lock time. Life is difficult.
Fortunately, engineers have developed a new kind of PLL that doesn’t have the intrinsic limitations: the so-called fractional-N PLLs. The idea is simple. A fractional-N PLL allows integer values for the N divider as well as fractional ones. That’s a great idea. This way the same channel spacing can be achieved with higher values for the PFD frequency, giving a quicker lock time and far lower noise.
Let’s take back the previous example and assume that you have a fractional-N chip enabling a 0.01-resolution for N. You could then use a PFD frequency of 100 kHz (compared to 1 kHz with the integer-N PLL). An output frequency of 500 MHz + 1 kHz would be achieved with N = 5,000.01, the loop filter would be 50 kHz and not 500 Hz (providing a 100× improvement on lock time), and the noise due to the PFD would be reduced by 20log(100) = 40 dB.
This seems magical, but nothing is free. No one has found a way to build an actual perfect fractional frequency divider on silicon (at megahertz or gigahertz speeds). The trick used by actual fractional-N chips is to dynamically switch N between two integer values (e.g., 5,000 and 5,001 in this example) with a time ratio proportional to the designed fractional value. Note that 99% of the time with N = 5,000 and 1% of the time with N = 5,001 gives roughly a 5000.01 divide ratio. Unfortunately, this introduces some noise on the PFD output, which could generate nasty spurious frequencies on the output spectrum. Moreover, due to implementation restrictions, a fractional-N chip is more complex to program and can’t generate an arbitrary frequency.
