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Feature Article

Issue #209 December 2007

THE DARKER SIDE
Are You Locked?
A PLL Primer
by Robert Lacoste

Start | VCO Basics | PLL Basics | Integer or Fractional? | PLL Design | Silicon Trends | It's Your Turn! | Sources & PDF

PLL BASICS

With a VCO, you can easily generate any frequency by applying the correct DC voltage at its input. Because there isn’t a feedback loop, this use of a VCO is called open-loop. It is effectively used in some important applications (e.g., a local oscillator for a 20-year-old high-end spectrum analyzer). However, such an open-loop VCO has two fundamental drawbacks. The first is that its frequency will drift over time and temperature because the components used in the VCO are never 100% stable. Its frequency will also drift if the power supply voltage or output load changes (the two last effects are called “pushing” and “pulling” in VCO specifications). The second drawback is that any voltage noise on the DC control input will generate frequency-domain noise, which means bad phase noise characteristics.

Using a PLL is an efficient way to wrap an imperfect VCO in a circuit in order to lock its output frequency on a more stable reference frequency, as well as to reduce its phase noise.

PLLs date back to the 1930s when the first homodyne RF receivers were designed. Homodyne receivers are zero intermediate frequency receivers, mixing the antenna signal with an oscillator tuned exactly as the transmitter carrier frequency. Because the local oscillators were unstable, a way to constantly retune it was needed. British engineers built an automatic correction loop based on a measurement of the actual receiver output. The design, based on an idea published in 1932 by the French scientist H. de Bellescise, was probably the first PLL.

Figure 6—The architecture of a PLL is built around a phase detector that drives a voltage-controlled oscillator through a filtering stage. The output of the VCO is then looped back to the phase detector and compared to a reference frequency. Dividers enable you to change the frequency ratio between the reference and output. So-called “fractional-N” PLLs have the same architecture but allow noninteger dividers.

The overall architecture of a PLL can be seen in Figure 6. It is quite simple. The key idea is to compare a reference frequency (F_IN, divided by a constant R if needed) and the actual output frequency of a VCO (F_OUT, divided by a constant N if needed), using a block called a phase/frequency detector (PFD). The error signal is then filtered and used to drive the VCO frequency control input. How does it work? The loop is stabilized when both phase detector inputs have equal frequencies (and in phase), meaning F_IN/R is FOUT/N. Simply multiplying both sides of the equation by N gives F_OUT = N × F_IN/R. If the VCO drifts and its frequency increases, the phase detector will see the change and decrease its output voltage, which will then reduce the VCO frequency until it is back equal to N × F_IN/R. The same will happen if the drift is in the other direction. The frequency output of the VCO will stay locked on the value N × F_IN/R thanks to the loop. That’s why we call it a PLL. The frequency at which the phase detector is working (F_IN/R is equal to F_OUT/N) is called the PFD frequency and is a fundamental choice in the design of a PLL.

I already covered the architecture of a VCO, and I’m sure you know that a digital frequency divider is easily built with a binary counter. The other building block of a PLL is the phase frequency detector. The first PLL chips used an exclusive OR gate as the detector. The gate provides a stable rectangular signal if both inputs are frequency and phase locked, which is transformed into an average DC value with a good low-pass filter, which could then drive the VCO. The only issue is that because the filter is not perfect, the PFD frequency “leaks” to the VCO input, which gives a noisy output. Modern PLL chips are based on charge pump PFDs, which are far cleaner. Such a PFD injects small amounts of positive or negative current in a capacitor if the frequency is drifting and stays quiet if both signals are locked. You will find a detailed explanation of charge pump PFDs in the Texas Instruments application note SWRA029.

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